Data storage device and operating method thereof

ABSTRACT

Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.

CROSS-REFERENCES TO RELATED APPLICATION

This patent document claims priority to Korean patent application number10-2019-0001712, filed on Jan. 7, 2019, which is incorporated herein byreference in its entirety for all purposes.

TECHNICAL FIELD

The disclosed technology generally relates to electronic devices, andmore particularly, to data storage devices.

BACKGROUND

In recent years, the paradigm for computer environments has changed fromdesktop computing to ubiquitous computing, which enables the use ofcomputer systems anytime and everywhere. As a result, the use ofportable electronic devices such as mobile phones, digital cameras, andlaptop computers has been increasing rapidly. Typically, portableelectronic devices use data storage devices that employ memory devices,which may be used to store data used in the portable electronic devices.

Data storage devices using memory devices have no mechanically drivenunits and exhibit good stability and endurance, fast information accessrate, and low power consumption. Such data storage devices may includeuniversal serial bus (USB) memory devices, memory cards having variousinterfaces, universal flash storage (UFS) devices, solid state drives(SSDs), and the like.

SUMMARY

Embodiments of the disclosed technology, among other features andbenefits, provide data storage devices capable of effectively performinga read fail recovery operation.

In an embodiment of the present disclosure, a data storage device mayinclude: a nonvolatile memory device including a plurality of pagegroups; a data buffer configured to store data to be stored in datapages of each of the plurality of page groups; an exclusive OR (XOR)parity buffer configured to store an XOR parity to be stored in an XORparity page of each of the plurality of page groups; and a processorconfigured to, when program-in-progress pages are present in a pagegroup including a read fail page in which read-failed data is stored inread fail occurrence during performing of a read operation according toa read request from a host, control data and an XOR parity correspondingto the program-in-progress pages to be read from the data buffer and theXOR parity buffer and control an error of the read-failed data to berecovered using data corresponding to program-completed pages other thanthe read fail page, and the data and the XOR parity read from the databuffer and the XOR parity buffer.

In an embodiment of the present disclosure, a data storage device mayinclude: a nonvolatile memory device including a page group in whichprogram-completed pages and program-in-progress pages are mixed; abuffer memory configured to buffer data and an exclusive OR (XOR) parityto be stored in pages of the page group; a recovery circuit configuredto recover an error of read-failed data; and a processor configured tocontrol the recovery circuit to read data and an XOR paritycorresponding to the program-in-progress pages from the buffer memoryand to recover the error of the read-failed data using datacorresponding to remaining program-completed pages other than a page inwhich the read-failed data is stored among the program-completed pages,and the data and the XOR parity read from the buffer memory.

In an embodiment of the present disclosure, an operating method of adata storage device includes performing a read operation on anonvolatile memory device in response to a read request from a host;confirming whether or not one or more program-in-progress pages arepresent in a page group including a page in which read-failed data isstored in read fail occurrence; reading, when the program-in-progresspages are present in the page group, data and an exclusive OR (XOR)parity corresponding to the program-in-progress pages from a buffermemory; and recovering an error of the read-failed data using datacorresponding to program-completed pages other than the page in whichthe read-failed data is stored, and the data and the XOR parity readfrom the buffer memory.

In an embodiment of the present disclosure, a data storage device mayinclude: a nonvolatile memory device including a plurality of pagegroups; a data buffer configured to store data to be stored in datapages of each of the plurality of page groups; an exclusive OR (XOR)parity buffer configured to store an XOR parity to be stored in an XORparity page of each of the plurality of page groups; and a processorconfigured to, when program-uncompleted pages are present in a pagegroup including a read fail page in which read-failed data is stored inread fail occurrence during performing of a read operation according toa read request from a host, control data and an XOR parity correspondingto the program-uncompleted pages to be read from the data buffer and theXOR parity buffer and control an error of the read-failed data to berecovered using data corresponding to program-completed pages other thanthe read fail page, and the data and the XOR parity read from the databuffer and the XOR parity buffer.

In an embodiment of the present disclosure, a data storage device mayinclude: a nonvolatile memory device including a page group in whichprogram-completed pages and program-uncompleted pages are mixed; abuffer memory configured to buffer data and an exclusive OR (XOR) parityto be stored in pages of the page group; a recovery circuit configuredto recover an error of read-failed data; and a processor configured tocontrol the recovery circuit to read data and an XOR paritycorresponding to the program-uncompleted pages from the buffer memoryand to recover the error of the read-failed data using datacorresponding to remaining program-completed pages other than a page inwhich the read-failed data is stored among the program-completed pages,and the data and the XOR parity read from the buffer memory.

In an embodiment of the present disclosure, an operating method of adata storage device includes performing a read operation on anonvolatile memory device in response to a read request from a host;confirming whether or not one or more program-uncompleted pages arepresent in a page group including a page in which read-failed data isstored in read fail occurrence; reading, when the program-uncompletedpages are present in the page group, data and an exclusive OR (XOR)parity corresponding to the program-uncompleted pages from a buffermemory; and recovering an error of the read-failed data using datacorresponding to program-completed pages other than the page in whichthe read-failed data is stored, and the data and the XOR parity readfrom the buffer memory.

In some embodiments described in the present document, in a read failoccurrence for a page group in which program-completed pages andprogram-in-progress pages are mixed, the read fail may be recovered byreading the data and XOR parity of the program-in-progress pages from abuffer memory. Thus, the read fail recovery operation may be furtherperformed more efficiently and quickly.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings; however, they may be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the example embodiments to those skilled in the art.

In the drawings, dimensions may be exaggerated for clarity ofillustration.

FIG. 1 is a diagram illustrating an exemplary configuration of a datastorage device, based on an embodiment of the presently disclosedtechnology.

FIG. 2 is a diagram illustrating an exemplary configuration of anonvolatile memory device, based on an embodiment of the presentlydisclosed technology.

FIG. 3A is a diagram illustrating an exemplary configuration of a memorycell array, based on an embodiment of the presently disclosedtechnology.

FIG. 3B is a diagram illustrating an exemplary configuration of a planeof FIG. 3A.

FIG. 4A is a circuit diagrams illustrating an example of memory blocks,based on an embodiment of the presently disclosed technology.

FIG. 4B is a circuit diagram illustrating another example of memoryblocks, based on an embodiment of the presently disclosed technology.

FIG. 5A is a diagram illustrating an example of quadruple level cell(QLC) program operations, based on an embodiment of the presentlydisclosed technology.

FIG. 5B is a diagram illustrating another example of quadruple levelcell (QLC) program operations, based on an embodiment of the presentlydisclosed technology.

FIG. 6A is a diagram illustrating an example of a threshold voltagedistribution of a page to which a first QLC program operation iscompleted, based on an embodiment of the presently disclosed technology.

FIG. 6B is a diagram illustrating another example of a threshold voltagedistribution of a page to which a second QLC program operation iscompleted, based on an embodiment of the presently disclosed technology.

FIG. 7A is a diagram illustrating an example of configurations of pagegroups, based on an embodiment of the presently disclosed technology.

FIG. 7B is a diagram illustrating another example of a configuration ofpage groups, based on an embodiment of the presently disclosedtechnology.

FIG. 8 is a diagram illustrating an example of a process of generatingand storing an XOR parity for data and transmitting the data and the XORparity to a nonvolatile memory device, based on an embodiment of thepresently disclosed technology.

FIG. 9A is a diagram illustrating an example of a page group in whichprogram-completed pages and program-in-progress pages are mixed, basedon an embodiment of the presently disclosed technology.

FIG. 9B is a diagram illustrating another example in which a read failfor program-completed pages occurs, based on an embodiment of thepresently disclosed technology.

FIG. 10A is a diagram illustrating an example of read fail recoveryoperations of a recovery circuit, based on an embodiment of thepresently disclosed technology.

FIG. 10B is a diagram illustrating another example of read fail recoveryoperations of a recovery circuit, based on an embodiment of thepresently disclosed technology.

FIG. 11 is a flowchart illustrating an example of an operating method ofa data storage device, based on an embodiment of the presently disclosedtechnology.

FIG. 12 is a diagram illustrating an example of a data processing systemincluding a solid state drive (SSD), based on an embodiment of thepresently disclosed technology.

FIG. 13 is a diagram illustrating an example of a controller illustratedin FIG. 12.

FIG. 14 is a diagram illustrating another example of a data processingsystem including a data storage apparatus, based on an embodiment of thepresently disclosed technology.

FIG. 15 is a diagram illustrating yet another example of a dataprocessing system including a data storage apparatus, based on anembodiment of the presently disclosed technology.

FIG. 16 is a diagram illustrating an example of a network systemincluding a data storage apparatus, based on an embodiment of thepresently disclosed technology.

FIG. 17 is a diagram illustrating an example of a two-stage foggy andfine write operation.

DETAILED DESCRIPTION

Semiconductor memory devices may be volatile or nonvolatile. Thevolatile semiconductor memory devices may perform read and writeoperations at high speeds, while contents stored therein may be lost atpower-off. The nonvolatile semiconductor memory devices may retaincontents stored therein even at power-off. The nonvolatile semiconductormemory devices may be used to store contents, which must be retainedregardless of whether they are powered.

Some embodiments of the disclosed technology provide methods, systemsand devices for efficiently performing a read-fail recovery operation ina nonvolatile memory device by reading data and/or XOR parity ofprogram-in-progress pages from a buffer memory.

In an example, the read-fail recovery operation is part of a chipkilloperation being performed to mitigate the effect of a read fail in NANDusing a foggy-fine scheme.

FIG. 1 is a diagram illustrating an example configuration of a datastorage device 10, based on an embodiment of the disclosed technology.

Referring to FIG. 1, the data storage device 10 may store data to beaccessed by a host (not illustrated in FIG. 1) such as a mobile phone,an MP3 player, a laptop computer, a desktop computer, a game player, atelevision (TV), or an in-vehicle infotainment system, and the like. Insome embodiments, the data storage device 10 may refer to a memorysystem.

In some embodiments, the data storage device 10 may be manufactured asany one among various types of storage devices according to an interfaceprotocol coupled to a host. For example, the data storage device 10 maybe configured as any one of various types of storage devices, including,but not limited to, a solid state drive (SSD), a multimedia card in theform of an MMC, an eMMC, an RS-MMC, and a micro-MMC, a secure digitalcard in the form of an SD, a mini-SD, and a micro-SD, a universal serialbus (USB) storage device, a universal flash storage (UFS) device, apersonal computer memory card international association (PCMCIA) cardtype storage device, a peripheral component interconnect (PCI) card typestorage device, a PCI-express (PCI-e) card type storage device, acompact flash (CF) card, a smart media card, a memory stick, and thelike.

In some embodiments, the data storage device 10 may be manufactured asany one of various types of packages. For example, the data storagedevice 10 may be manufactured as a package on package (POP), a system inpackage (SIP), a system on chip (SOC), a multi-chip package (MCP), achip on board (COB), a wafer-level fabricated package (WFP), or awafer-level stack package (WSP).

In some embodiments, the data storage device 10 may include anonvolatile memory device 100 and a controller 200.

In some embodiments, the controller 200 may control an overall operationof the data storage device 10 through the execution of firmware orsoftware. For example, the firmware or software may be stored in thenonvolatile memory device 100 and may be loaded into a memory (forexample, first buffer memory 230) in the controller 200 during bootingof the data storage device 10. The controller 200 may be implementedwith hardware or a combination of hardware and software.

In some embodiments, the controller 200 may include a host interface210, a processor 220, a first buffer memory 230, an error correctioncode (ECC) circuit 240, an exclusive OR (XOR) operation circuit 250, arecovery circuit 260, and a memory interface 270.

In an example, the host interface 210 may interface between a host andthe data storage device 10 according to a host protocol. For example,the host interface 210 may communicate with the host through a protocolthat includes a USB protocol, a UFS protocol, an MMC protocol, aparallel advanced technology attachment (PATA) protocol, a serialadvanced technology attachment (SATA) protocol, a small computer systeminterface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a PCIprotocol, and a PCI-e protocol.

In another example, the processor 220 may include a micro control unit(MCU) and/or a central processing unit (CPU). The processor 220 mayprocess a request transmitted from the host. To process the requesttransmitted from the host, the processor 220 may execute a code-typeinstruction or algorithm (for example, firmware) loaded into the firstbuffer memory 230 and control internal function blocks such as the hostinterface 210, the first buffer memory 230, the ECC circuit 240, the XORoperation circuit 250, the recovery circuit 260, the memory interface270, and the nonvolatile memory device 100.

In yet another example, the processor 220 may generate control signalsfor controlling an operation of the nonvolatile memory device 100 basedon the requests transmitted from the host, and further provide thegenerated control signals to the nonvolatile memory device 100 throughthe memory interface 270.

In yet another example, the first buffer memory 230 may include a staticrandom access memory (SRAM), but this is not limited thereto. Thefirmware executed by the processor 220 may be loaded into the firstbuffer memory 230. The first buffer memory 230 may store data (forexample, metadata) required for executing the firmware. For example, thefirst buffer memory 230 may be operate as a working memory of theprocessor 220. In an embodiment, the firmware executed by the processor220 and the metadata required for the executing the firmware may beloaded into a memory (not shown in FIG. 1) separately coupled to theprocessor 220 from the first buffer memory 230.

In yet another example, the first buffer memory 230 may store an XORparity used and/or generated by the XOR operation circuit 250. The XORparity may include a plurality of bits generated through performing ofan XOR operation on program data to be stored in the nonvolatile memorydevice 100. For example, the XOR parity may be a parity generatedthrough performing of an XOR operation on program data having apredetermined size or length. The XOR parity may be used for the readfail recovery operation which corrects an error of read-failed data inread fail occurrence. Here, the read fail may refer to an ECC decodingfailure of read data read out from the nonvolatile memory device 100.

In yet another example, the ECC circuit 240 may perform an ECC encodingoperation which generates parity data of program data to be transmittedfrom a host to the nonvolatile memory device 100. The ECC circuit 240may also perform an ECC decoding operation which has the ability todetect and correct an error of the read data read out from thenonvolatile memory device 100 based on the parity data corresponding tothe read data.

For example, the ECC circuit 240 may generate the parity data byECC-encoding the program data received from the host and provide encodeddata including the program data and the parity data to the nonvolatilememory device 100 through the memory interface 270. The ECC circuit 240may detect and correct an error included in the read data using theparity data included in the encoded data read out from the nonvolatilememory device 100 in response to a read request of the host. The ECCcircuit 240 may correct the error when a number of detected error bitsis less than or equal to a predefined number of error corresponding tothe error-correcting capability of the ECC circuit 240 The ECC circuit240 may provide the error-corrected data to the host through the hostinterface 210.

In yet another example, the XOR operation circuit 250 may generate theXOR parity for the program data by performing an XOR operation on theprogram data having a predetermined size or length. When the parity bitgenerated in the ECC circuit 240 is a parity bit of the program datacorresponding to a minimum program unit, the XOR parity generated in theXOR operation circuit 250 may be a parity bit for a data group includingtwo or more program data of the minimum program unit. For example, theparity bit may be used in performing an ECC decoding operation on theread data read out from the nonvolatile memory device 100 and the XORparity may be used in performing a recovery operation for recovering anerror of the read data (for example, read-failed data) in the event ofan ECC decoding failure.

In yet another example, the XOR operation circuit 250 may generate theXOR parity for the program data temporarily stored in a second buffermemory 280 and transmit the generated XOR parity to the first buffermemory 230. The first buffer memory 230 may store the XOR paritytransmitted from the XOR operation circuit 250.

In yet another example, the recovery circuit 260 may be configured torecover from an error of the read data (for example, the read-faileddata) in the event of an ECC decoding failure. For example, the recoverycircuit 260 may recover the error of the read-failed data by performingan XOR operation on the remaining data other than the read-failed datain a data group including the read-failed data and an XOR paritycorresponding to the corresponding data group.

In yet another example, the memory interface 270 may control thenonvolatile memory device 100 based on instructions from the processor220. The memory interface 270 may refer to a memory controller. Thememory interface 270 may provide control signals to the nonvolatilememory device 100. The control signals may include a command CMD, anaddress ADDR, an operation control signal (CTRL), and the like forcontrolling the nonvolatile memory device 100. The memory interface 270may provide data (for example, program data) to the nonvolatile memorydevice 100 or receive data (for example, read data) from the nonvolatilememory device 100.

In yet another example, the second buffer memory 280 may be configuredto include a data buffer (DB) (not shown in FIG. 1) which temporarilystores program data which is to be transmitted from a host to thenonvolatile memory device 100 or read data which is read out from thenonvolatile memory device 100 and to be transmitted to the host. Thesecond buffer memory 280 may include a dynamic random access memory(DRAM), but this is not limited thereto.

In some embodiments, as illustrated in FIG. 1, the second buffer memory280 is positioned outside of the controller 200. In other embodiments,the second buffer memory 280 may be located inside the controller 200.The program data temporarily stored in the second buffer memory 280 maybe retained in the second buffer memory 280 until the storage of theprogram data in the nonvolatile memory device 100 is completed.

In yet another example, the nonvolatile memory device 100 may operate asa storage medium for the data storage device 10. The nonvolatile memorydevice 100 may be one of various types of nonvolatile memory devices,which include, but are not limited to, a NAND flash memory device, a NORflash memory device, a ferroelectric random access memory (FRAM) using aferroelectric capacitor, a magnetic random access memory (MRAM) using atunneling magneto-resistive (TMR) layer, a phase-change random accessmemory (PRAM) using a chalcogenide alloy, and a resistive random accessmemory (RERAM) using a transition metal compound.

FIG. 2 is a diagram illustrating an example configuration of thenonvolatile memory device 100 of FIG. 1.

As shown in FIG. 2, the nonvolatile memory device 100 may include amemory cell array 110, a row decoder 120, a program/read circuit 130, acolumn decoder 140, a page buffer 150, a voltage generator 160, acontrol logic 170, and an input/output (I/O) circuit 180.

In an example, the memory cell array 110 may include a plurality ofmemory cells (not shown in FIG. 2) arranged in regions in which aplurality of word lines (WL) and a plurality of bit lines (BL) crosseach other perpendicularly.

Each of the memory cells in the memory cell array 110 may be at leastone of a single level cell (SLC), in which a single bit data (forexample, 1-bit data) is to be stored, a multi-level cell (MLC) in which2-bit data is to be stored, a triple level cell (TLC) in which 3-bitdata is to be stored, and a quadruple level cell (QLC) in which 4-bitdata is to be stored. The memory cell array 110 may include at least oneor more memory cells from among the group that includes the SLC, theMLC, the TLC, and the QLC. The memory cell array 110 may include memorycells arranged in a two-dimensional (2D) horizontal structure or memorycells arranged in a 3D vertical structure.

The row decoder 120 may be coupled to the memory cell array 110 throughthe word lines WL. The row decoder 120 may be operated according tocontrol of the control logic 170. The row decoder 120 may decode a rowaddress X_ADDR provided from the control logic 170 and select and driveat least one word line WL of the word lines WL based on a decodingresult. The row decoder 120 may provide an operation voltage Vopprovided from the voltage generator 160 to the selected word line WL.

The program/read circuit 130 may be coupled to the memory cell array 110through the bit lines BL. The program/read circuit 130 may includeprogram/read circuits (not shown in FIG. 2) corresponding to the bitlines BL. The program/read circuit 130 may be operated according tocontrol of the control logic 170. The program/read circuit 130 mayinclude a program driver WD configured to program data in the memorycells and a sense amplifier SA configured to amplify data read from thememory cells. The program/read circuit 130 may perform a program andread operations on selected memory cells by providing a current pulse ora voltage pulse to the memory cells selected through the row decoder 120and the column decoder 140 among the memory cells of the memory cellarray 110.

The column decoder 140 may be operated according to control of thecontrol logic 170. The column decoder 140 may decode a column addressY_ADDR provided from the control logic 170. The column decoder 140 maycouple the program/read circuits of the program/read circuit 130corresponding to the bit lines BL to the page buffer 150 based on adecoding result.

The page buffer 150 may be configured to temporarily store data which isprovided from the memory interface 270 of the controller 200 and is tobe programmed in the memory cell array 110, and data which is read outfrom the memory cell array 110 and is to be provided to the memoryinterface 270 of the controller 200. The page buffer 150 may be operatedaccording to control of the control logic 170.

The voltage generator 160 may generate various voltages for performing aprogram, read, and erase operations on the memory cell array 110 basedon a voltage control signal CTRL_vol provided from the control logic170. The voltage generator 160 may generate driving voltages Vop fordriving the plurality of word lines WL and the plurality of bit linesBL. The voltage generator 160 may generate at least one or morereference voltages for reading out data stored in a memory cell MC.

The control logic 170 may output various control signals for programmingdata DATA in the memory cell array 110 or reading out data DATA from thememory cell array 110, based on a command CMD, an address ADDR, or acontrol signal CTRL received from the controller 200. The variouscontrol signals output from the control logic 170 may be provided to therow decoder 120, the program/read circuit 130, the column decoder 140,the page buffer 150, and the voltage generator 160. Accordingly, thecontrol logic 170 may entirely control the various operations performedin the nonvolatile memory device 100.

For example, the control logic 170 may generate an operation controlsignal CTRL_op based on the command CMD and the control signal CTRL andprovide the generated operation control signal CTRL_op to theprogram/read circuit 130. The control logic 170 may provide the rowaddress X_ADDR and the column address Y_ADDR included in the addressADDR to the row decoder 120 and the column decoder 140.

The I/O circuit 180 may be configured to receive the command CMD, theaddress ADDR, and the data DATA provided from the controller 200 orprovide the data DATA read out from the memory cell array 110 to thecontroller 200. The I/O circuit 180 may output the command CMD and theaddress ADDR received from the controller 200 to the control logic 170and output the data DATA received from the controller 200 to the pagebuffer 150. The I/O circuit 180 may output data DATA received from thepage buffer 150 to the controller 200. The I/O circuit 180 may beoperated according to control of the control logic 170.

FIG. 3A is a diagram illustrating an example configuration of a memorycell array 110, based on an embodiment of the disclosed technology, andFIG. 3B is a diagram illustrating an example configuration of a plane ofFIG. 3A.

As shown in FIG. 3A, the memory cell array 110 may include a pluralityof dies, denoted DIE1 to DIEp. In some embodiments, the dies DIE1 toDIEp may be memory chips. Each of the plurality of dies DIE1 to DIEp mayinclude a plurality of planes PNE1 to PNEq. As shown in FIG. 3B, each ofthe plurality of planes PNE1 to PNEq may include a plurality of memoryblocks BLK1 to BLKi and each of the plurality of memory blocks BLK1 toBLKi may include a plurality of pages PG1 to PGj.

FIGS. 4A and 4B are circuit diagrams illustrating examples of memoryblocks, based on embodiments of the disclosed technology. FIG. 4A is acircuit diagram illustrating an example of a memory block BLKa, whichincludes memory cells arranged in a 2D manner, and FIG. 4B is a circuitdiagram illustrating another example of a memory block BLKb, whichincludes memory cells arranged in a 3D manner. For example, each of thememory blocks BLK1 to BLKi illustrated in FIG. 3B may be implementedusing the circuit illustrated in FIG. 4A or 4B, but the configuration ofthe memory block is not limited thereto.

As shown in FIG. 4A, the memory block BLKa may have a 2D horizontalstructure. For example, the memory block BLKa may include a plurality ofbit lines BL1 to BLm arranged to be spaced in a first direction and aplurality of word lines WL1 to WLn arranged to be spaced in a seconddirection that is substantially perpendicular to the first direction. Inan example, the first direction may be an X-axis direction and thesecond direction may be a Y-axis direction. In another example, thefirst direction may be the Y-axis direction and the second direction maybe the X-axis direction.

The memory block BLKa may include a plurality of cell strings CS coupledto the plurality of bit lines BL1 to BLm. In an example, the cellstrings CS may have the same circuit configuration as each other. Forclarity, the memory block BLKa will be described in the context of asingle cell string CS.

The cell string CS may include a plurality of memory cells MC1 to MCnand drain and source select transistors (DST and SST, respectively)coupled between the bit line BL1 and a common source line CSL. Forexample, the cell string CS may include the drain select transistor DSTcoupled to a drain select line DSL, the plurality of memory cells MC1 toMCn coupled to the plurality of word lines WL1 to WLn, and the sourceselect transistor SST coupled to a source select line SSL.

As shown in FIG. 4A, a plurality of memory cells coupled to the sameword line may referred to as a page (PG) unit. The program operation orthe read operation may be simultaneously performed on the plurality ofmemory cells coupled to the same word line, but this is not limitedthereto.

As shown in FIG. 4B, the memory block BLKb may have a 3D verticalstructure.

In some embodiments, the memory block BLKb may include a plurality ofbit lines BL1 to BLm arranged to be spaced in a first direction, aplurality of cell strings CS11 to CS1 k˜CSm1 to CSmk coupled to theplurality of bit lines BL1 to BLm and arranged to be spaced in a seconddirection, and a plurality of word lines WL1 to WLn arranged to bespaced in a third direction (with the first, second and third directionsbeing substantially perpendicular to each other). In an example, thefirst direction may be an X-axis direction, the second direction may bea Y-axis direction, and the third direction may be a Z-axis direction,but this is not limited thereto.

In an example, K cell strings may be coupled to each of m bit lines andthus m×k cell strings may be arranged in the memory block BLKb. Here, n,m, and k are integers greater than or equal to 1.

In another example, each of the plurality of cell strings CS11 to CS1k˜CSm1 to CSmk may include at least one source select transistor SST,first to n-th memory cells MC1 to MCn, and at least one drain selecttransistor DST. The source select transistor SST in each cell string maybe coupled between the common source line CSL and the memory cells MC1to MCn.

In yet another example, source select transistors SST of cell stringsarranged on the same line in the X-axis direction may be coupled to thesame source select line. For example, the source select transistors SSTof a plurality of first cell strings CS11 to CSm1 coupled to the bitlines BL1 to BLm may be coupled to a first source select line SSL1.Similarly, the source select transistors SST in the plurality of secondto k-th cell strings CS12 to CSm2˜CS1 k to CSmk coupled to the bit linesBL1 to BLm may be coupled to second to k-th source select lines SSL2 toSSLk.

In yet another example, drain select transistors DST of the cell stringsarranged on the same line in the X-axis direction may be coupled to thesame drain select line. For example, the drain select transistors DST ofthe plurality of first cell strings CS11 to CSm1 coupled to the bitlines BL1 to BLm may be coupled to a first drain select line DSL1.Similarly, the drain select transistors DST in the plurality of secondto k-th cell strings CS12 to CSm2˜CS1 k to CSmk coupled to the bit linesBL1 to BLm may be coupled to second to k-th drain select lines DSL2 toDSLk.

In yet another example, the first to n-th memory cells MC1 to MCn ineach of the plurality of cell strings CS11 to CS1 k˜CSm1 to CSmk may becoupled in series between the source select transistor SST and the drainselect transistor DST.

In yet another example, the first to n-th memory cells MC1 to MCn ineach of the plurality of cell strings CS11 to CS1 k˜CSm1 to CSmk may becoupled to first to n-th word lines WL1 to WLn. The memory cells coupledto the cell strings arranged on the same line in the X-axis directionand coupled to the same word line may be referred to as a page (PG)unit.

In yet another example, as shown in FIG. 4B, the first memory cells MC1coupled to the first cell strings CS11 to CSm1 arranged on the same linein the X-axis direction and coupled to the first word line WL1 may referto a first-first page PG11. Similarly, the first memory cells MC1coupled to the second to k-th cell strings CS12 to CSm2˜CS1 k to CSmkarranged on the same line in the X-axis direction and coupled to thefirst word line WL1 may refer to first-second to first-k-th pages PG12to PG1 k. For example, in the 3D vertical structure illustrated in FIG.4B, a plurality of pages may be coupled to one word line, but this isnot limited thereto.

In yet another example, K pages may be coupled to each of the word linesWL1 to WLn and thus n×k pages may be arranged in the memory block BLKb.The number of pages in each of the word lines WL1 to WLn may be changedaccording to the number of cell strings coupled to each of the bit linesBL1 to BLm.

An exemplary program operation for the memory block having the 3Dvertical structure illustrated in FIG. 4B will now be described.

FIGS. 5A and 5B are diagrams illustrating an example QLC programoperation, based on embodiments of the disclosed technology. Forsimplification of the drawings and convenience of the description, it isassumed that a memory block BLKo includes four word lines WL1 to WL4 andfour pages sets PG11 to PG14, PG21 to PG24, PG31 to PG34, and PG41 toPG44 are coupled to the four word lines WL1 to WL4. For example, thefour first pages PG11 to PG14 may be coupled to the first word line WL1,four second pages PG21 to PG24 may be coupled to the second word lineWL2, four third pages PG31 to PG34 may be coupled to the third word lineWL3, and four fourth pages PG41 to PG44 may be coupled to the fourthword line WL4.

As shown in FIG. 5A, the QLC program operation for the memory block BLKomay start from the first-first page PG11 of the first word line WL1 andmay be terminated in the fourth-fourth page PG44 of the fourth word lineWL4.

In an example, the QLC program operation on the memory block BLKo may beperformed in order of the first QLC program (1, 2, 3, 4) for the firstpages PG11 to PG14 of the first word line WL1, followed by the first QLCprogram (5, 6, 7, 8) for the second pages PG21 to PG24 of the secondword line WL2, followed by the second QLC program (9, 10, 11, 12) forthe first pages PG11 to PG14 of the first word line WL1, followed by thefirst QLC program (13, 14, 15, 16) for the third pages PG31 to PG34 ofthe third word line WL3, followed by the second QLC program (17, 18, 19,20) for the second pages PG21 to PG24 of the second word line WL2,followed by the first QLC program (21, 22, 23, 24) for the fourth pagesPG41 to PG44 of the fourth word line WL4, followed by the second QLCprogram (25, 26, 27, 28) for the third pages PG31 to PG34 of the thirdword line WL3, and finally the second QLC program (29, 30, 31, 32) forthe fourth pages PG41 to PG44 of the fourth word line WL4. Accordingly,the QLC program operation for all the pages PG11 to PG44, coupled to thefirst to fourth word lines WL1 to WL4, may be normally completed.

In this example, the first QLC program operation performed on the firstto fourth word lines WL1 to WL4 may be referred to as a foggy (orcoarse) program operation and the second QLC program operation performedon the first to fourth word lines WL1 to WL4 may be referred to as afine program operation. With respect to the same page, data to be storedin the first QLC program operation and data to be stored in the secondQLC program operation may be the same as each other, but this is notlimited thereto.

As the capacity of the nonvolatile memory device 100 increases, theamount of data to be stored in one memory cell also increases. In recentyears, the use of a quadruple level cell (QLC) method which storesfour-bit data in one memory cell has increased. With the increasedintegration of the memory cell array 100, the space between signal lines(word lines and bit lines) is being reduced. This causes interference,due to a word line on which the program operation is being performed,with other word lines adjacent thereto, for example, a previous wordline to which the program operation is completed. As a result, the datapre-stored in memory cells coupled to the previous word line may becorrupted. For example, the corruption of the pre-stored data may meanthat the threshold voltage distributions of the memory cells coupled tothe previous word line are deformed.

To reform (or reconstitute) the threshold voltage distributions of firstmemory cells coupled to a first word line to the desired thresholdvoltage distributions for performing QLC operations, an exemplary QLCprogram operation has to be performed. This exemplary QLC programoperation includes a first QLC program operation (for example, foggyprogram operation) which stores a first data in the first memory cellscoupled to the first word line, another first QLC program operation (forexample, foggy program operation) which stores a second data in secondmemory cells coupled to a word line (for example, a second word line)next to the first word line, and then a second QLC program operation(for example, fine program operation) which stores the first data in thefirst memory cells of the first word line again.

For example, the threshold voltage distributions of the memory cells onwhich the first QLC program operation is performed may not be clearlydistinguishable from each other as illustrated in FIG. 6A. For example,the threshold voltage distributions of the memory cells may overlap witheach other. The threshold voltage distributions of the memory cells onwhich the second QLC program operation is performed may be clearlydistinguished from each other as illustrated in FIG. 6B. The thresholdvoltage distributions of the memory cells may be completely separatedfrom each other without any overlapping portion.

Accordingly, since the threshold voltage distributions of the memorycells coupled to a previous word line are deformed due to theinterference by the program operation performed on next word line, thefirst QLC program operation on the previous word line may be performedso that the threshold voltage distributions of the memory cells areclose to the desired form, the first QLC program operation on the nextword line may be performed, and then the second QLC program operation,which programs the same data in the previous word line again, may beperformed on the previous word line so that the threshold voltagedistributions of the memory cells coupled to the previous word line mayreach the desired form.

As shown in FIG. 5B, the QLC program operation for the memory block BLKomay start from the first-first page PG11 of the first word line WL1 andmay be terminated in the fourth-fourth page PG44 of the fourth word lineWL4, similar to the QLC program operation shown in FIG. 5A. However, theQLC program operation shown in FIG. 5B is different from the QLC programoperation of FIG. 5A in that the QLC program method of FIG. 5Bsequentially performs the first QLC program operation on a plurality ofpages (for example, the first pages PG11 to PG14) coupled to a firstword line (for example, the first word line WL1) and then alternatelyperforms the first QLC program operation (or the second QLC programoperation) on a plurality of pages coupled to next word line and aplurality of pages coupled to a previous word line one page by one page.

In an example, referring to FIG. 5B, the QLC program operation on thememory block BLKo may be performed in order of the first QLC program (1,2, 3, 4) for the first pages PG11 to PG14 of the first word line WL1,followed by the first QLC program (5) for the second-first page PG21 ofthe second word line WL2, followed by the second QLC program (6) for thefirst-first page PG11 of the first word line WL1, followed by the firstQLC program (7) for the second-second page PG22 of the second word lineWL2, followed by the second QLC program (8) for the first-second pagePG12 of the first word line WL1, followed by the first QLC program (9)for the second-third page PG23 of the second word line WL2, followed bythe second QLC program (10) for the first-third page PG13 of the firstword line WL1, followed by the first QLC program (11) for thesecond-fourth page PG24 of the second word line WL2, and finally thesecond QLC program (12) for the first-fourth page PG14 of the first wordline WL1.

In another example, the QLC program operation on the memory block BLKomay be performed in order of the first QLC program (13) for thethird-first page PG31 of the third word line WL3, followed by the secondQLC program (14) for the second-first page PG21 of the second word lineWL2, followed by the first QLC program (15) for the third-second pagePG32 of the third word line WL3, followed by the second QLC program (16)for the second-second page PG22 of the second word line WL2, followed bythe first QLC program (17) for the third-third page PG33 of the thirdword line WL3, followed by the second QLC program (18) for thesecond-third page PG23 of the second word line WL2, followed by thefirst QLC program (19) for the third-fourth page PG34 of the third wordline WL3, and finally the second QLC program (20) for the second-fourthpage PG24 of the second word line WL2.

In yet another example, the QLC program operation on the memory blockBLKo may be performed in order of the first QLC program (21) for thefourth-first page PG41 of the fourth word line WL4, followed by thesecond QLC program (22) for the third-first page PG31 of the third wordline WL3, followed by the first QLC program (23) for the fourth-secondpage PG42 of the fourth word line WL4, followed by the second QLCprogram (24) for the third-second page PG32 of the third word line WL3,followed by the first QLC program (25) for the fourth-third page PG43 ofthe fourth word line WL4, followed by the second QLC program (26) forthe third-third page PG33 of the third word line WL3, followed by thefirst QLC program (27) for the fourth-fourth page PG44 of the fourthword line WL4, followed by the second QLC program (28) for thethird-fourth page PG34 of the third word line WL3, and finally thesecond QLC program (29, 30, 31, 32) for the fourth-first tofourth-fourth pages PG41-PG44 of the fourth word line WL4. In someembodiments, the program operation illustrated in FIG. 5A may refer to afour-string program operation and the program operation illustrated inFIG. 5B may refer to one-string program operation.

FIGS. 7A and 7B are diagrams illustrating example configurations of apage group, based on embodiments of the disclosed technology. Forsimplification of the drawings and convenience of the description, it isassumed that the memory cell array 110 includes four dies DIE1 to DIE4,each of the four dies DIE1 to DIE4 includes one plane which includes onememory block, and the memory block in each of the four dies DIE1 to DIE4includes a plurality of pages PG11 to PG14, PG21 to PG24, PG31 to PG34,and PG41 to PG44. For example, it is assumed that each of the first tofourth dies DIE1 to DIE4 is configured of one memory block including theplurality of pages PG11 to PG14, PG21 to PG24, PG31 to PG34, and PG41 toPG44.

As shown in FIG. 7A, the memory cell array 110 may include four pagegroups XORPG1 to XORPG4. Each of the four page groups XORPG1 to XORPG4may include 16 pages. For example, the first page group XORPG1 mayinclude the first pages PG11 to PG14 of the first die DIE1, the firstpages PG11 to PG14 of the second die DIE2, the first pages PG11 to PG14of the third die DIE3, and the first pages PG11 to PG14 of the fourthdie DIE4. For example, in the context of FIGS. 5A and 5B, the first pagegroup XORPG1 may be configured to include four first pages PG11 to PG14coupled to the first word line WL1 in each of the first to fourth diesDIE1 to DIE4 and the fourth page group XORPG4 may be configured toinclude four fourth pages PG41 to PG44 coupled to the fourth word lineWL4 in each of the first to fourth dies DIE1 to DIE4. In someembodiments, and although not shown in FIG. 7A, the second and thirdpage groups may be configured to have the same configuration as thefirst page group XORPG1. For example, the second page group XORPG2 maybe configured to include four second pages PG21 to PG24 coupled to thesecond word line WL2 in each of the first to fourth dies DIE1 to DIE4and the third page group XORPG3 may be configured to include four thirdpages PG31 to PG34 coupled to the third word line WL3 in each of thefirst to fourth dies DIE1 to DIE4.

When the page groups are configured to have the exemplary configurationillustrated in FIG. 7A, an XOR parity corresponding to data (forexample, user data) stored in pages other than the last page of the lastdie DIE may be stored in the last page PG of the last die DIE among theplurality of pages included in each page group. For example, in thefirst page group XORPG1, the user data may be stored in the first pagesPG11 to PG14 of the first to third dies DIE1 to DIE3 and the first-firstto first-third pages PG11 to PG13 of the fourth die DIE4 and the XORparity for the user data may be stored in the first-fourth page PG14 ofthe fourth die DIE4. Accordingly, the ‘page group’ described here mayalso be understood as the ‘XOR parity group’.

As shown in FIG. 7B, the memory cell array 110 may include 16 pagegroups XORPG1 to XORPG16. Each of the 16 page groups XORPG1 to XORPG16may include four pages.

For example, the first page group XORPG1 may include the first-firstpage PG11 of the first die DIE1, the first-first page PG11 of the seconddie DIE2, the first-first page PG11 of the third die DIE3, and thefirst-first page PG11 of the fourth die DIE4. Referring to FIGS. 5A, 5Band 7B, the first page group XORPG1 may be configured to include thefirst-first pages PG11 of the first pages PG11 to PG14 coupled to thefirst word line WL1 in the first to fourth dies DIE1 to DIE4, the secondpage group XORPG2 may be configured to include the first-second pagesPG12 of the first pages PG11 to PG14 coupled to the first word line WL1in the first to fourth dies DIE1 to DIE4, the third page group XORPG3may be configured to include the first-third pages PG13 of the firstpages PG11 to PG14 coupled to the first word line WL1 in the first tofourth dies DIE1 to DIE4, and the fourth page group XORPG4 may beconfigured to include the first-fourth pages PG14 of the first pagesPG11 to PG14 coupled to the first word line WL1 in the first to fourthdies DIE1 to DIE4.

Referring to FIGS. 5A, 5B, and 7B, the 13-th page group XORPG13 may beconfigured to include the fourth-first pages PG41 of the fourth pagesPG41 to PG44 coupled to the fourth word line WL4 in the first to fourthdies DIE1 to DIE4, the 14-th page group XORPG14 may be configured toinclude the fourth-second pages PG42 of the fourth pages PG41 to PG44coupled to the fourth word line WL4 in the first to fourth dies DIE1 toDIE4, the 15-th page group XORPG15 may be configured to include thefourth-third pages PG43 of the fourth pages PG41 to PG44 coupled to thefourth word line WL4 in the first to fourth dies DIE1 to DIE4, and the16-th page group XORPG16 may be configured to include the fourth-fourthpages PG44 of the fourth pages PG41 to PG44 coupled to the fourth wordline WL4 in the first to fourth dies DIE1 to DIE4.

In some embodiments, and although not shown in FIG. 7B, the 5-th to12-th page groups may be configured to have the same configuration asthe first page group XORPG1.

In some embodiments, when the page groups are configured to have theconfiguration illustrated in FIG. 7B, the XOR parity corresponding tothe user data stored in remaining pages other than a page of the lastdie DIE may be stored in the page PG of the last die DIE among theplurality of pages included in each page group. For example, in thefirst page group XORPG1, the user data may be stored in the first-firstpages PG11 of the first to third dies DIE1 to DIE3 and the XOR parityfor the user data may be stored in the first-first page PG11 of thefourth die DIE4.

The configurations of the page groups illustrated in FIGS. 7A and 7B aremerely exemplary and may be modified according to the needs or designchange. When the total size of the memory cell array 110 is limited, thenumber of pages included in the page group may be reduced as the numberof page groups is increased and the number of pages included in the pagegroup may be increased as the number of page groups is reduced.

FIG. 8 is a diagram illustrating an example process of generating andstoring an XOR parity for data and transmitting the data and the XORparity to a nonvolatile memory device, based on an embodiment of thedisclosed technology. This exemplary process is described with referenceto FIG. 8 with FIG. 7B. For clarity, the page group has the exampleconfiguration shown in FIG. 7B.

As shown in FIG. 8, the second buffer memory 280 may store program datareceived from a host, for example, program data DATA111, DATA112, andDATA113 (hereinafter, referred to as ‘first program data (or first data)DATA111’, ‘second program data (or second data) DATA112’, and ‘thirdprogram data (or third data) DATA113’)) to be stored in the first-firstpages PG11 of the first to third dies DIE1 to DIE3 in the first pagegroup XORPG1. The second buffer memory 280 may sequentially transmit thefirst to third program data DATA111, DATA112, and DATA113 stored thereinto the nonvolatile memory device 100. The second buffer memory 280 mayretain the first to third program data DATA111, DATA112, and DATA113stored therein until the storage of the first to third program dataDATA111, DATA112, and DATA113 in the first-first pages PG11 of the firstto third dies DIE1 to DIE3 in the first page group XORPG1 is completedand/or confirmed.

The XOR operation circuit 250 may generate an XOR parity XORP11 byperforming an XOR operation on the first to third program data DATA111,DATA112, and DATA113 stored in the second buffer memory 280 and transmitthe generated XOR parity XORP11 to the first buffer memory 230. In someembodiments, the XOR parity XORP11 may be an XOR-operated value ofcorresponding bits of the first to third program data DATA111, DATA112,and DATA113. Accordingly, the XOR parity XORP11 may comprise the samenumber of bits as that of each of the first to third program dataDATA111, DATA112, and DATA113 (since XORP11 is a bit-wise XOR operationon the first, second and third program data).

The first buffer memory 230 may store the XOR parity XORP11 receivedfrom the XOR operation circuit 250. The first buffer memory 230 maytransmit the stored XOR parity to the nonvolatile memory device 100. Thefirst buffer memory 230 may retain the XOR parity XORP11 stored thereinuntil the storage of the XOR parity XORP11 in the first-first page PG11of the fourth die DIE4 in the first page group XORPG1 is completedand/or confirmed.

The nonvolatile memory device 100 may perform a program operation whichstores the first to third program data DATA111, DATA112, and DATA113received from the second buffer memory 280 in the first-first pages PG11of the first to third dies DIE1 to DIE3 of the first page group XORPG1and stores the XOR parity XORP11 received from the first buffer memory230 in the first-first page PG11 of the fourth die DIE4 of the firstpage group XORPG1.

In some embodiments, and since the first to fourth dies DIE1 to DIE4 arephysically separated from each other, the nonvolatile memory device 100may not simultaneously program the first to third program data DATA111,DATA112, and DATA113 and the XOR parity XORP11 in the first-first pagesPG11 of the first to fourth dies DIE1 to DIE4 and thus, may sequentiallystore the first to third program data DATA111, DATA112, and DATA113 andthe XOR parity XORP11 in the first-first pages PG11 of the first tofourth dies DIE1 to DIE4 from the first-first page PG11 of the first dieDIE1.

FIG. 9A is a diagram illustrating an example page group in whichprogram-completed pages and program-in-progress pages are mixed, basedon an embodiment of the disclosed technology. FIG. 9B is a diagramillustrating an example that read fail for program-completed pagesoccurs, based on an embodiment of the disclosed technology.

As shown in FIG. 9A, the first-first pages PG11 of the first and seconddies DIE1 and DIE2 of the first page group XORPG1 may be‘program-completed pages’ in which the storage of the first and secondprogram data DATA111 and DATA112 is completed (denoted using a densedotted pattern in FIG. 9A). In an example, the ‘program-completed page’may refer to a page on which both the first QLC program (e.g., a foggyprogram operation) and the second QLC program (e.g., a fine programoperation) have been performed. The first-first pages PG11 of the thirdand fourth dies DIE3 and DIE4 of the first page group XORPG1 may be‘program-in-progress pages’ that the storage of the third program dataDATA113 and the XOR parity XORP11 is not completed (denoted using asparse dotted pattern in FIG. 9B). In an example, the‘program-in-progress page’ may refer to a page on which only the firstQLC program (e.g., a foggy program operation) is performed. In anotherexample, the ‘program-in-progress page’ may refer to a page on whichonly a first of at least two or more first QLC programs (e.g., a foggyprogram operation) is performed.

The foggy and fine program operations are further elucidated later inthe document in the context of FIG. 17.

Embodiments of the disclosed technology advantageously enable a readfail recovery operation (e.g., a chipkill recovery operation) to beperformed efficiently and quickly even in the presence ofprogram-in-progress pages by accessing the buffer memories that storethe data and/or parity that is current being read from theprogram-in-progress pages. In other words, leveraging the available dataand/or parity in the buffer memories (e.g., first buffer memory 230 andsecond buffer memory 280) ensures that the latency of the recoveryoperation is minimized since there is no need to wait for theprogram-in-process pages to becomes program-completed pages.

For example, it is assumed that a read request for the first-first pagePG11 of the second die DIE2 of the first page group XORPG1 is receivedfrom a host.

Although not shown in FIGS. 9A and 9B, the controller 200 may generate,in response to the read request from the host, a read command forreading out the second data DATA112 from the first-first page PG11 ofthe second die DIE2 of the first page group XORPG1 and transmit the readcommand to the nonvolatile memory device 100. The nonvolatile memorydevice 100 may read the second data DATA112 from the first-first pagePG11 of the second die DIE2 of the first page group XORPG1 based on theread command received from the controller 200 and transmit the readsecond data DATA112 to the controller 200.

The ECC circuit 240 of the controller 200 may perform ECC decoding onthe second data DATA112 received from the nonvolatile memory device 100and the controller 200 may transmit, upon an indication of ECC decodingsuccess, the error-corrected second data DATA112 to the host when theECC decoding is successful. On the other hand, when the ECC decodingfails, the controller 200 may determine that the read fail for thesecond data DATA112 has occurred and performs the read fail recoveryoperation for recovering the error of the second data DATA112 using therecovery circuit 260. For this example, the read fail for the seconddata DATA112 stored in the first-first page PG11 of the second die DIE2of the first page group XORPG1 is illustrated in FIG. 9B.

FIG. 10A is a diagram illustrating an example of a read fail recoveryoperation of a recovery circuit, based on an embodiment of the disclosedtechnology. In a typical error recovery operation of the read-faileddata, the data and the XOR parity stored in the remaining pages otherthan the page in which the read-failed data was stored (hereinafter,referred as ‘read fail page’) in the page group, including the read failpage, may be used in the error recovery operation. However, asillustrated in FIG. 10A, when the first page group XORPG1 is a pagegroup that includes both program-completed pages and program-in-progresspages, the data stored in the program-in-progress page of the first pagegroup XORPG1 may not be used in the error recovery of the read-failedsecond data DATA112.

In some embodiments, the error recovery on the read-failed second dataDATA112 may be performed using only the data stored in the pages of thefirst page group XORPG1, and a second QLC program is being performed onthe program-in-progress pages (e.g., the first-first page PG11 of thethird die DIE3 and the first-first page PG11 of the fourth die DIE4 arebeing processed). In this case, the program operation on theprogram-in-progress pages in the first page group XORPG1 must becompleted and only then the error recovery of the read-failed seconddata DATA112 may be performed. Thus, the time until the read failrecovery is completed may increase and the read fail recovery operationmay be adversely affected (e.g., performed inefficiently).

Embodiments of the disclosed technology, when the program-in-progresspages are present in the page group including the read fail page,provide for the data and the XOR parity stored in the second buffermemory 280 and the first buffer memory 230 to be used in the read failrecovery operation as the data and the XOR parity corresponding to theprogram-in-progress pages. Thus, the read fail recovery operation may beperformed more efficiently and quickly.

For example, and as shown in FIG. 10A, to perform the read fail recoveryoperation on the second data DATA112 stored in the first-first page PG11of the second die DIE2 of the first page group XORPG1, the recoverycircuit 260 has to read, from the first page group XORPG1, the firstdata DATA111 stored in the first-first page PG11 of the first die DIE1,the third data DATA113 stored in the first-first page PG11 of the thirddie DIE3, and the XOR parity stored in the first-first page PG11 of thefourth die DIE4.

Since the first-first pages PG11 of the third and fourth dies DIE3 andDIE4 of the first page group XORPG1 are the program-in-progress pages,the data of the corresponding first-first pages PG11 may not be used inthe read fail recovery operation.

Accordingly, the recovery circuit 260 according to the embodiment mayread the first data DATA111 from the first-first page PG11 of the firstdie DIE1 of the first page group XORPG1 in the memory cell array 110 ofthe nonvolatile memory device 100 and read the third data DATA113 andthe XOR parity XORP11 from the second buffer memory 280 and the firstbuffer memory 230, respectively. For example, the data and the XORparity stored in the pages for which the second QLC program is notcompleted may be read and used from the second buffer memory 280 and thefirst buffer memory 230 which stores (or retains) the corresponding dataand XOR parity for the program-in-progress pages.

The recovery circuit 260 may recover an error of the read-failed seconddata DATA112 by performing an XOR operation on corresponding bits of thefirst data DATA111, the third data DATA113, and the XOR parity XORP11.

FIG. 10B is a diagram illustrating another example of a read failrecovery operation of a recovery circuit, based on an embodiment of thedisclosed technology. As shown in FIG. 10B, the recovery circuit 260 mayperform the read fail recovery operation by reading out all the data(for example, the first data DATA111) of the program-completed page (forexample, the first-first page PG11 of the first die DIE1) and the data(for example, the third data DATA113 and the XOR parity XORP11) of theprogram-in-progress pages (for example, the first-first pages PG11 ofthe third and fourth dies DIE3 and DIE4) from the buffer memories 230and 280. In this case, the data of the program-completed page may not bedeleted from the second buffer memory 280 and may be retained in thesecond buffer memory 280 until all the programs for the other pages ofthe same page group are completed.

FIG. 11 is a flowchart illustrating an exemplary operating method of adata storage device, based on an embodiment of the disclosed technology.

In operation S1101, the controller 200 may instruct the nonvolatilememory device 100 to perform a read operation in response to a readrequest received from a host. For example, the processor 220 of thecontroller 200 may generate a read command to be provided to thenonvolatile memory device 100 based on the read request received fromthe host and provide the generated read command to the nonvolatilememory device 100 through the memory interface 270. The nonvolatilememory device 100 may perform the read operation which reads out datafrom the memory cell array 110 according to the read command receivedfrom the controller 200 and provide the read data to the controller 200.

In operation S1103, the controller 200 may determine whether or not aread fail occurs during the read operation. For example, the ECC circuit240 of the controller 200 may perform ECC decoding on the read datareceived from the nonvolatile memory device 100 through the memoryinterface 270. When the ECC decoding is successful, the ECC circuit 240may provide information indicating that the ECC decoding is successfulto the processor 220 and simultaneously may store the error-correctedread data in a read buffer (not shown) included in the first buffermemory 230 or the second buffer memory 280. When the ECC decoding hasfailed, the ECC circuit 240 may provide information indicating that theECC decoding is failed to the processor 220. The processor 220 maydetermine whether or not the read fail occurs based on the informationreceived from the ECC circuit 240. When it is determined that the readfail has not occurred, the process may proceed to operation S1119,wherein the read data is transmitted to the host. When it is determinedthat the read fail has occurred, the process may proceed to operationS1105.

In operation S1105, the processor 220 may determine whether or not theprogram-in-progress pages are present in a page group including a page(for example, read fail page) in which read-failed data is stored.

In operation S1107, the processor 220 may determine whether or not theprogram-in-progress pages are present in the page group including theread fail page based on the determination in operation S1105. When theprogram-in-progress pages are not present, the process may proceed tooperation S1115. When the program-in-progress pages are present, theprocess may proceed to operation S1109.

In operation S1109, the processor 220 may instruct the recovery circuit260 to read data and an XOR parity corresponding to theprogram-in-progress pages from the second buffer memory 280 as a databuffer and the first buffer memory 230 as an XOR parity buffer.

In operation S1111, the processor 220 may instruct the recovery circuit260 to recover an error of read-failed data using data of theprogram-completed pages other than the read fail page in the page groupincluding the read fail page, and the data and the XOR parity of theprogram-in-progress pages read from the first and second buffer memories230 and 280 in operation S1109.

In some embodiments, the recovery circuit 260 may read the data of theprogram-completed pages from the nonvolatile memory device 100 or thesecond buffer memory 280 according to control of the processor 220. Therecovery circuit 260 may recovery the error of the read-failed data byperforming an XOR operation on corresponding bits of the data of theprogram-completed pages, and the data and the XOR parity of theprogram-in-progress pages. The recovery circuit 260 may store theerror-recovered data in a read buffer (not shown) included in at leastone of the first buffer memory 230 or the second buffer memory 280.

In operation S1113, the processor 220 may transmit the error-recovereddata stored in the read buffer to the host through the host interface210.

In operation S1115, the processor 220 may control the recovery circuit260 to read data and an XOR parity corresponding to all the remainingpages other than the read fail page in the page group from thenonvolatile memory device 100.

In operation S1117, the recovery circuit 260 may recover the error ofthe read-failed data by performing an XOR operation on correspondingbits of the data and XOR parity read from the nonvolatile memory device100 in operation S1115 based on instructions from the processor 220, andstore the error-recovered data in a read buffer (not shown) included inat least one of the first buffer memory 230 or the second buffer memory280.

In operation S1119, the processor 220 may transmit the error-correctedread data stored in a read buffer (not shown) included in the firstbuffer memory 230 or the second buffer memory 280 in operation S1103 tothe host through the host interface 210.

The exemplary method illustrated in FIG. 11 demonstrates the efficacy ofembodiments of the disclosed technology in speeding up the read failrecovery process in the presence of program-in-progress pages. In someembodiments, the program-in-progress pages may include pages for whichthe foggy program operation has been completed, but the fine programoperation is still in progress. In other embodiments, theprogram-in-progress pages may include pages for which a first foggyprogram operation has been completed, but a second or subsequent foggyprogram operation is still in progress.

FIG. 12 is a diagram illustrating an example of a data processing systemthat includes a solid state drive (SSD), based on an embodiment of thedisclosed technology. As shown in FIG. 12, a data processing system 2000may include a host apparatus 2100 and a SSD 2200.

In some embodiments, the SSD 2200 may include a controller 2210, abuffer memory device 2220, nonvolatile memory devices 2231 to 223 n, apower supply 2240, a signal connector 2250, and a power connector 2260.

In an example, the controller 2210 may control an overall operation ofthe SSD 2220.

In some embodiments, the buffer memory device 2220 may temporarily storedata to be stored in the nonvolatile memory devices 2231 to 223 n. Thebuffer memory device 2220 may temporarily store data read from thenonvolatile memory devices 2231 to 223 n. The data temporarily stored inthe buffer memory device 2220 may be transmitted to the host apparatus2100 or the nonvolatile memory devices 2231 to 223 n based oninstructions from the controller 2210.

In some embodiments, the nonvolatile memory devices 2231 to 223 n may beused as a storage medium of the SSD 2200. The nonvolatile memory devices2231 to 223 n may be coupled to the controller 2210 through a pluralityof channels CH1 to CHn. In an example, one or more nonvolatile memorydevices may be coupled to one channel. The nonvolatile memory devicescoupled to the one channel may be coupled to the same signal bus and thesame data bus.

In some embodiments, the power supply 2240 may provide a power PWR inputthrough the power connector 2260 to the inside of the SSD 2200. Thepower supply 2240 may include an auxiliary power supply 2241, whichsupplies power to ensure that the SSD 2200 is normally terminated evenwhen a sudden (or abrupt) power-off occurs. In an example, the auxiliarypower supply 2241 may include large capacity capacitors capable ofcharging the power PWR.

In some embodiments, the controller 2210 may exchange a signal SGL withthe host apparatus 2100 through the signal connector 2250. The signalSGL may include a command, an address, data, and the like. The signalconnector 2250 may be one of various types of connectors, and based onan interfacing method between the host apparatus 2100 and the SSD 2200.

FIG. 13 is a diagram illustrating an example of the controller 2210 ofFIG. 12. As shown in FIG. 13, the controller 2210 may include a hostinterface 2211, a controller 2212, a random access memory (RAM) 2213, anerror correction code (ECC) component 2214, and a memory interface 2215.

In some embodiments, the host interface 2211 may perform interfacingfunctions between the host apparatus 2100 and the SSD 2200 according toa protocol of the host apparatus 2100. In an example, the host interface2211 may communicate with the host apparatus 2100 through any one of asecure digital protocol, a universal serial bus (USB) protocol, amultimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, apersonal computer memory card international association (PCMCIA)protocol, a parallel advanced technology attachment (PATA) protocol, aserial advanced technology attachment (SATA) protocol, a small computersystem interface (SCSI) protocol, a serial attached SCSI (SAS) protocol,a peripheral component interconnection (PCI) protocol, a PCI Express(PCI-E) protocol, and a universal flash storage (UFS) protocol. Inanother example, the host interface 2211 may perform a disc emulationfunction that the host apparatus 2100 recognizes the SSD 2200 as ageneral-purpose data storage apparatus, for example, a hard disc driveHDD.

In some embodiments, the controller 2212 may analyze and process thesignal SGL input from the host apparatus 2100. In an example, thecontroller 2212 may control operations of internal functional blocksbased on firmware and/or software that defines the operation of the SDD2200. In another example, the RAM 2213 may be operated as a workingmemory for executing the firmware or software.

In some embodiments, the ECC component 2214 may generate parity data forthe data to be transferred to the nonvolatile memory devices 2231 to 223n. The generated parity data may be stored in the nonvolatile memorydevices 2231 to 223 n together with the data. In other embodiments, theECC component 2214 may detect errors for data read from the nonvolatilememory devices 2231 to 223 n based on the parity data. When detectederrors are within a correctable range (e.g., the number of detectederrors are fewer than the error-correcting capability of the ECC), theECC component 2214 may correct the detected errors.

In some embodiments, the memory interface 2215 may provide a controlsignal such as a command and/or an address to the nonvolatile memorydevices 2231 to 223 n based on instructions from the controller 2212.The memory interface 2215 may exchange data with the nonvolatile memorydevices 2231 to 223 n based on instructions from the controller 2212.For example, the memory interface 2215 may provide data stored in thebuffer memory device 2220 to the nonvolatile memory devices 2231 to 223n or provide data read from the nonvolatile memory devices 2231 to 223 nto the buffer memory device 2220.

FIG. 14 is a diagram illustrating an example of a data processing systemincluding a data storage apparatus, based on an embodiment of thedisclosed technology. As shown in FIG. 14, a data processing system 3000may include a host apparatus 3100 and a data storage apparatus 3200.

In some embodiments, the host apparatus 3100 may be implemented as aboard (e.g., a printed circuit board (PCB)). Although not shown in FIG.14, the host apparatus 3100 may include internal functional blocksconfigured to perform functions of the host apparatus 3100.

In some embodiments, the host apparatus 3100 may include a connectionterminal 3110 such as a socket, a slot, or a connector. The data storageapparatus 3200 may be mounted on the connection terminal 3110.

In some embodiments, the data storage apparatus 3200 may be implementedas a board (e.g., a PCB). In an example, the data storage apparatus 3200may refer to a memory module or a memory card. In another example, thedata storage apparatus 3200 may include a controller 3210, a buffermemory device 3220, nonvolatile memory devices 3231 to 3232, a powermanagement integrated circuit (PMIC) 3240, and a connection terminal3250.

In some embodiments, the controller 3210 may control an overalloperation of the data storage apparatus 3200. For example, thecontroller 3210 may have the same configuration as the controller 2210illustrated in FIG. 13.

In some embodiments, the buffer memory device 3220 may temporarily storedata to be stored in the nonvolatile memory devices 3231 and 3232. In anexample, the buffer memory device 3220 may temporarily store data readfrom the nonvolatile memory devices 3231 and 3232. In another example,the data temporarily stored in the buffer memory device 3220 may betransmitted to the host apparatus 3100 or the nonvolatile memory devices3231 and 3232 according to control of the controller 3210.

In some embodiments, the nonvolatile memory devices 3231 and 3232 may beused as a storage medium of the data storage apparatus 3200.

In some embodiments, the PMIC 3240 may provide power through theconnection terminal 3250 to the inside of the data storage apparatus3200. In an example, the PMIC 3240 may manage the power of the datastorage apparatus 3200 based on instructions from the controller 3210.

In some embodiments, the connection terminal 3250 may be coupled to theconnection terminal 3110 of the host apparatus 3100. A signal such as acommand, an address, data and/or power may be transmitted between thehost apparatus 3100 and the data storage apparatus 3200 through theconnection terminal 3250. The connection terminal 3250 may be configuredin various forms according to an interface between the host apparatus3100 and the data storage apparatus 3200. The connection terminal 3250may be arranged in any one side of the data storage apparatus 3200.

FIG. 15 is a diagram illustrating an example of a data processing systemthat includes a data storage apparatus, based on an embodiment of thedisclosed technology. As shown in FIG. 15, a data processing system 4000may include a host apparatus 4100 and a data storage apparatus 4200.

In some embodiments, the host apparatus 4100 may be implemented as aboard (e.g., a PCB). Although not shown in FIG. 15, the host apparatus4100 may include internal functional blocks configured to performfunctions of the host apparatus 4100.

In some embodiments, the data storage apparatus 4200 may be implementedin a surface mounting packaging form. In an example, the data storageapparatus 4200 may be mounted on the host apparatus 4100 through asolder ball 4250. In another example, the data storage apparatus 4200may include a controller 4210, a buffer memory device 4220, and anonvolatile memory device 4230.

In some embodiments, the controller 4210 may control an overalloperation of the data storage apparatus 4200. The controller 4210 may behave the same configuration as the controller 2210 illustrated in FIG.13.

In some embodiments, the buffer memory device 4220 may temporarily storedata to be stored in the nonvolatile memory device 4230. In an example,the buffer memory device 4220 may temporarily store data read from thenonvolatile memory device 4230. In another example, the data temporarilystored in the buffer memory device 4220 may be transmitted to the hostapparatus 4100 or the nonvolatile memory device 4230 through control ofthe controller 4210.

In some embodiments, the nonvolatile memory device 4230 may be used as astorage medium of the data storage apparatus 4200.

FIG. 16 is a diagram illustrating an example of a network system 5000that includes a data storage apparatus, based on an embodiment of thedisclosed technology. As shown in FIG. 16, the network system 5000 mayinclude a server system 5300 and a plurality of client systems 5410 to5430 which are coupled through a network 5500.

In some embodiments, the server system 5300 may serve data in responseto requests of the plurality of client systems 5410 to 5430. In anexample, the server system 5300 may store data provided from theplurality of client systems 5410 to 5430. In another example, the serversystem 5300 may provide data to the plurality of client systems 5410 to5430.

In some embodiments, the server system 5300 may include a host apparatus5100 and a data storage apparatus 5200. The data storage apparatus 5200may be the data storage device 10 of FIG. 1, the data storage apparatus2200 of FIG. 12, the data storage apparatus 3200 of FIG. 14, or the datastorage apparatus 4200 of FIG. 15.

FIG. 17 is a diagram illustrating an example of a two-stage foggy andfine write operation. As shown in FIG. 17, three intermediatedistributions FMA, FMB, and FMC are written (foggy write), and then theintermediate distributions FMA to FMC are used to write the final targetthreshold voltage distributions A, B, and C (fine write). In thisscheme, the verify operations of the intermediate distributions FMA,FMB, and FMC are performed in the above pseudo-negative sense scheme.

The foggy write is a rough write of the upper page data/lower page data.The fine write is an accurate write of the upper page data/lower pagedata. Specifically, the foggy write operation and the fine writeoperation are performed as a two-stage write operation.

As shown in FIG. 17, a write operation in a four-level storage schemeincluding the foggy write operation and the fine write operation will bedescribed. First, starting with the state (1) in which all memory cellsare erased, the foggy write operation to a memory cell (2) is performed.Referring to FIG. 17, the foggy write operation is a write operation inwhich a verify voltage VAV′, VBV′, or VCV′ smaller than the lower limitsof the final target threshold voltage distributions E, A, B, and C isused to obtain the intermediate distribution FMA, FMB, or FMC.

The fine write operation to the memory cell (3) is then performed. Thefine write operation uses the verify voltage VAV, VBV, or VCV equal tothe lower limits of the final target threshold voltage distributions E,A, B, and C to shift the intermediate distribution FMA, FMB, or FMC inthe positive direction to obtain the threshold voltage distribution E,A, B, or C. Specifically, the verify voltages VAV′, VBV′, and VCV′ forthe foggy write are lower than the respective verify voltages VAV, VBV,and VCV for the fine write. Likewise, the lower limits of theintermediate distributions FMA, FMB, and FMC are smaller than the lowerlimits of the respective threshold voltage distributions A, B, and C.Note that the upper limits of the intermediate distributions FMA, FMB,and FMC may be higher than the upper limits of the respective thresholdvoltage distributions A, B, and C.

The intermediate distributions FMA, FMB, and FMC are written before thethreshold voltage distributions A, B, and C are written, and are notassigned with the final data. Specifically, the memory cell reading isset to read voltages RA, RB, and RC that fall between the upper andlower limits of two of the threshold voltage distributions E and A to C.

Embodiments of the disclosed technology provide methods, systems anddevices for improving an efficiency of a read fail recovery operation.An exemplary data storage device includes a nonvolatile memory deviceincluding a plurality of page groups; a data buffer configured to storedata to be stored in data pages of each of the plurality of page groups;an exclusive OR (XOR) parity buffer configured to store an XOR parity tobe stored in an XOR parity page of each of the plurality of page groups;and a processor configured to, when program-in-progress pages arepresent in a page group including a read fail page in which read-faileddata is stored in read fail occurrence during performing of a readoperation according to a read request from a host, control data and anXOR parity corresponding to the program-in-progress pages to be readfrom the data buffer and the XOR parity buffer and control an error ofthe read-failed data to be recovered using data corresponding toprogram-completed pages other than the read fail page, and the data andthe XOR parity read from the data buffer and the XOR parity buffer.

In some embodiments, the data storage device further includes an XORoperation circuit configured to generate the XOR parity by performing anXOR operation on the data to be stored in the data pages of each of theplurality of page groups; and a recovery circuit configured to recoverthe error of the read-failed data by performing an XOR operation oncorresponding bits of data corresponding to the program-completed pages,and the data and the XOR parity read from the data buffer and the XORparity buffer. In other embodiments, the processor controls the recoverycircuit to read the data corresponding to the program-completed pagesother than the read fail page from the nonvolatile memory device. In yetother embodiments, the processor controls the recovery circuit to readthe data corresponding to the program-completed pages other than theread fail page from the data buffer. In these embodiments, when theprogram-in-progress pages are not present in the page group includingthe read fail page, the processor controls the recovery circuit torecover the error of the read-failed data by reading data and an XORparity corresponding to remaining pages other than the read fail page inthe page group from the nonvolatile memory device.

In some embodiments, each of the plurality of page groups includes aplurality of dies, and the pages included in each page group include onepage coupled to the same word line in each of the dies. In otherembodiments, each of the plurality of page groups includes a pluralityof dies, and the pages included in each page group include a pluralityof pages coupled to the same word line in each of the dies.

Another exemplary data storage device includes a nonvolatile memorydevice including a page group in which program-completed pages andprogram-in-progress pages are mixed; a buffer memory configured tobuffer data and an exclusive OR (XOR) parity to be stored in pages ofthe page group; a recovery circuit configured to recover an error ofread-failed data; and a processor configured to control the recoverycircuit to read data and an XOR parity corresponding to theprogram-in-progress pages from the buffer memory and to recover theerror of the read-failed data using data corresponding to remainingprogram-completed pages other than a page in which the read-failed datais stored among the program-completed pages, and the data and the XORparity read from the buffer memory.

In some embodiments, the buffer memory includes a data buffer configuredto buffer the data to be stored in the pages of the page group; and anXOR parity buffer configured to buffer the XOR parity. In someembodiments, the data storage device further includes an XOR operationcircuit configured to generate the XOR parity by performing an XORoperation on the data buffered in the data buffer

In some embodiments, the recovery circuit recovers the error of theread-failed data by performing an XOR operation on corresponding bits ofthe data corresponding to the remaining program-completed pages, and thedata and the XOR parity read from the buffer memory. In otherembodiments, the processor controls the recovery circuit to read thedata corresponding to the remaining program-completed pages from thenonvolatile memory device. In yet other embodiments, the processorcontrols the recovery circuit to read the data corresponding to theremaining program-completed pages from the buffer memory.

A method for operating a data storage device, the method includesperforming a read operation on a nonvolatile memory device in responseto a read request from a host; confirming whether or not one or moreprogram-in-progress pages are present in a page group including a pagein which read-failed data is stored in read fail occurrence; reading,when the program-in-progress pages are present in the page group, dataand an exclusive OR (XOR) parity corresponding to theprogram-in-progress pages from a buffer memory; and recovering an errorof the read-failed data using data corresponding to program-completedpages other than the page in which the read-failed data is stored, andthe data and the XOR parity read from the buffer memory.

In some embodiments, the method further includes before the recoveringof the error of the read-failed data, reading the data corresponding tothe program-completed pages from the nonvolatile memory device. In otherembodiments, the method further includes before the recovering of theerror of the read-failed data, reading the data corresponding to theprogram-completed pages from the buffer memory.

In some embodiments, the confirming of whether or not the one or moreprogram-in-progress pages are present includes reading data and an XORparity corresponding to remaining pages other than the page in which theread-failed data is stored among pages of the page group when theprogram-in-progress pages are not present in the page group.

In some embodiments, the recovering of the error of the read-failed dataincludes performing an XOR operation on corresponding bits of datacorresponding to the program-completed pages, and the data and the XORparity read from the buffer memory.

In some embodiments, the program-completed pages are pages on which botha first program operation and a second program operation are performed;and the program-in-progress pages are pages on which the first programoperation is performed and the second program operation is notperformed.

While the disclosed technology has been shown and described withreference to certain exemplary embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the disclosed technology as defined by the appended claims and theirequivalents. Therefore, the scope of the disclosed technology should notbe limited to the above-described exemplary embodiments but should bedetermined by not only the appended claims but also the equivalentsthereof.

In the above-described embodiments, all steps may be selectivelyperformed or part of the steps and may be omitted. In each embodiment,the steps are not necessarily performed in accordance with the describedorder and may be rearranged. The embodiments disclosed in thisspecification and drawings are only examples to facilitate anunderstanding of the disclosed technology, and the disclosed technologyis not limited thereto. That is, it should be apparent to those skilledin the art that various modifications can be made on the basis of thetechnological scope of the disclosed technology.

Meanwhile, the exemplary embodiments of the disclosed technology havebeen described in the drawings and specification. Although specificterminologies are used here, those are only to explain the embodimentsof the disclosed technology. Therefore, the disclosed technology is notrestricted to the above-described embodiments and many variations arepossible within the spirit and scope of the disclosed technology. Itshould be apparent to those skilled in the art that variousmodifications can be made on the basis of the technological scope of thedisclosed technology in addition to the embodiments disclosed herein.

What is claimed is:
 1. A data storage device comprising: a nonvolatilememory device including a plurality of page groups; a data bufferconfigured to store data to be stored in data pages of each of theplurality of page groups; an exclusive OR (XOR) parity buffer configuredto store an XOR parity to be stored in an XOR parity page of each of theplurality of page groups; and a processor configured to, whenprogram-in-progress pages are present in a page group including a readfail page in which read-failed data is stored in read fail occurrenceduring performing of a read operation according to a read request from ahost, control data and an XOR parity corresponding to theprogram-in-progress pages to be read from the data buffer and the XORparity buffer and control an error of the read-failed data to berecovered using data corresponding to program-completed pages other thanthe read fail page, and the data and the XOR parity read from the databuffer and the XOR parity buffer, wherein the program-completed pagesare pages on which both a first program operation and a second programoperation are performed, wherein the program-in-progress pages are pageson which the first program operation is performed and the second programoperation is not performed, wherein a threshold voltage distribution ofthe program-in-progress pages does not reach a final target thresholdvoltage distribution, and wherein a threshold voltage distribution ofthe program-completed pages has the final target threshold voltagedistribution.
 2. The data storage device of claim 1, further comprisingan XOR operation circuit configured to generate the XOR parity byperforming an XOR operation on the data to be stored in the data pagesof each of the plurality of page groups.
 3. The data storage device ofclaim 1, further comprising a recovery circuit configured to recover theerror of the read-failed data by performing an XOR operation oncorresponding bits of data corresponding to the program-completed pages,and the data and the XOR parity read from the data buffer and the XORparity buffer.
 4. The data storage device of claim 3, wherein theprocessor controls the recovery circuit to read the data correspondingto the program-completed pages other than the read fail page from thenonvolatile memory device.
 5. The data storage device of claim 3,wherein the processor controls the recovery circuit to read the datacorresponding to the program-completed pages other than the read failpage from the data buffer.
 6. The data storage device of claim 3,wherein when the program-in-progress pages are not present in the pagegroup including the read fail page, the processor controls the recoverycircuit to recover the error of the read-failed data by reading data andan XOR parity corresponding to remaining pages other than the read failpage in the page group from the nonvolatile memory device.
 7. The datastorage device of claim 1, wherein each of the plurality of page groupsincludes a plurality of dies, and the pages included in each page groupinclude one page coupled to the same word line in each of the dies. 8.The data storage device of claim 1, wherein each of the plurality ofpage groups includes a plurality of dies, and the pages included in eachpage group include a plurality of pages coupled to the same word line ineach of the dies.
 9. A data storage device comprising: a nonvolatilememory device including a page group in which program-completed pagesand program-in-progress pages are mixed; a buffer memory configured tobuffer data and an exclusive OR (XOR) parity to be stored in pages ofthe page group; a recovery circuit configured to recover an error ofread-failed data; and a processor configured to control the recoverycircuit to read data and an XOR parity corresponding to theprogram-in-progress pages from the buffer memory and to recover theerror of the read-failed data using data corresponding to remainingprogram-completed pages other than a page in which the read-failed datais stored among the program-completed pages, and the data and the XORparity read from the buffer memory, wherein the program-completed pagesare pages on which both a first program operation and a second programoperation are performed, wherein the program-in-progress pages are pageson which the first program operation is performed and the second programoperation is not performed, wherein a threshold voltage distribution ofthe program-in-progress pages does not reach a final target thresholdvoltage distribution, and wherein a threshold voltage distribution ofthe program-completed pages has the final target threshold voltagedistribution.
 10. The data storage device of claim 9, wherein the buffermemory includes; a data buffer configured to buffer the data to bestored in the pages of the page group; and an XOR parity bufferconfigured to buffer the XOR parity.
 11. The data storage device ofclaim 10, further comprising an XOR operation circuit configured togenerate the XOR parity by performing an XOR operation on the databuffered in the data buffer.
 12. The data storage device of claim 9,wherein the recovery circuit recovers the error of the read-failed databy performing an XOR operation on corresponding bits of the datacorresponding to the remaining program-completed pages, and the data andthe XOR parity read from the buffer memory.
 13. The data storage deviceof claim 9, wherein the processor controls the recovery circuit to readthe data corresponding to the remaining program-completed pages from thenonvolatile memory device.
 14. The data storage device of claim 9,wherein the processor controls the recovery circuit to read the datacorresponding to the remaining program-completed pages from the buffermemory.
 15. An operating method of a data storage device comprising:performing a read operation on a nonvolatile memory device in responseto a read request from a host; confirming whether or not one or moreprogram-in-progress pages are present in a page group including a pagein which read-failed data is stored in read fail occurrence; reading,when the program-in-progress pages are present in the page group, dataand an exclusive OR (XOR) parity corresponding to theprogram-in-progress pages from a buffer memory; and recovering an errorof the read-failed data using data corresponding to program-completedpages other than the page in which the read-failed data is stored, andthe data and the XOR parity read from the buffer memory, wherein theprogram-completed pages are pages on which both a first programoperation and a second program operation are performed, wherein theprogram-in-progress pages are pages on which the first program operationis performed and the second program operation is not performed, whereina threshold voltage distribution of the program-in-progress pages doesnot reach a final target threshold voltage distribution, and wherein athreshold voltage distribution of the program-completed pages has thefinal target threshold voltage distribution.
 16. The method of claim 15,further comprising: before the recovering of the error of theread-failed data, reading the data corresponding to theprogram-completed pages from the nonvolatile memory device.
 17. Themethod of claim 15, further comprising: before the recovering of theerror of the read-failed data, reading the data corresponding to theprogram-completed pages from the buffer memory.
 18. The method of claim15, wherein the confirming of whether or not the one or moreprogram-in-progress pages are present includes reading data and an XORparity corresponding to remaining pages other than the page in which theread-failed data is stored among pages of the page group when theprogram-in-progress pages are not present in the page group.
 19. Themethod of claim 15, wherein the recovering of the error of theread-failed data includes performing an XOR operation on correspondingbits of data corresponding to the program-completed pages, and the dataand the XOR parity read from the buffer memory.